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description the A1174 is a micro-power, hall-effect latch for use in portable devices that employ rotational detection systems, and have a power supply voltage between 1.65 and 3.5 v. the device has a single push-pull output structure and requires no external pull-up resistor for reliable operation. when a sufficient positive magnetic field is present on the device, the device output transitions to the low state and is latched in this state until a negative field of sufficient strength latches the device output into the high state. the latched output is ideal when using multiple sensors in rotational speed and direction sensing systems (for example, track ball and scroll bar systems in portable devices). the device includes an innovative clocking scheme that satisfies the micro-power needs of almost any application, including track balls for pdas and cell phones. using the external_clk and dual_clk pins as described in this datasheet, the device can be set into various working modes. in dual clock mode, the device switches between predefined slow and fast sampling rates. the average current consumption of the device is extremely low when rotation is not detected. in external clock mode, the user sets the clock rate for the device to achieve the required on and off times for controlling average power. this user-determined clocking also helps to A1174-ds features and benefits ? micro-power latch operation ? 1.65 to 3.5 v battery operation ? push-pull output eliminates the need for an external pull- up resistor ? user configured, internally or externally controlled sample and sleep periods ? floating the two clock pins results in the use of a fixed sampling clock internal to the sensor ? toggling the clock pins allows the user to control the sampling and sleep times of the sensor for extreme low power operation ? external control of the clock pins allows the user to implement synchronous sampling of multiple sensors in direction detection systems ? chopper stabilization ? superior temperature stability ? extremely low switchpoint drift ? insensitive to physical stress ? solid state reliability ? small size ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications continued on the next page? package: 6-contact mlp/dfn (suffix ew) not to scale A1174 1.5 mm 2 mm 0.40 mm 0 magnetic flux density A1174 output on off off on on +b b op b op b op b rp b rp b rp +v ?b figure 1. timing diagram for output switching
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com description (continued) vdd nc vout dual_clk gnd external_clk pad 6 5 4 1 2 3 pin-out diagram terminal list number name function 1 vdd supply voltage 2 nc no connect 3 vout output 4 external_clk in combination with dual_clk , allows external control of the device sampling period and duty cycle 5 gnd ground 6 dual_clk in combination with external_clk , drives the part in dual clock mode selection guide part number packing* A1174eewlt-t 3000 pieces per 7-inch reel *contact allegro ? for additional packing options achieve synchronous clocking of multiple devices. this allows a defined phase relationship between the output transitions of each device in direction detection systems. improved stability is made possible through dynamic offset cancellation using chopper stabilization, which reduces the residual offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. solid state reliability is provided by integrating, on a single silicon chip, a hall-voltage generator, a small-signal amplifier, chopper stabilization, a latch, and a mosfet output. the device package is a 6-contact, 1.5 mm 2 mm, 0.40 mm nominal overall height mlp/dfn, with exposed pad for enhanced thermal dissipation. it is lead (pb) free, with 100% matte tin leadframe plating. absolute maximum ratings characteristic symbol notes rating units forward supply voltage v dd 5.0 v reverse supply voltage v rdd ?0.3 v output voltage v out 5.0 v reverse output voltage v rout ?0.3 v external_clk and dual_clk pins input voltage v in 5.0 v external_clk and dual_clk pins reverse input voltage v rin ?0.3 v continuous output current i out(sink) ?1 ma i out(source) 1ma magnetic flux density* b unlimited g operating ambient temperature t a range e ?40 to 85 c maximum junction temperature t j (max) 165 c storage temperature t stg ?65 to 170 c *1g = 0.1 mt (millitesla) (top view)
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram vdd gnd amp vout input decoder sample control block internal clock latch external_clk dual_clk
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics valid over full operating voltage and ambient temperature ranges (unless otherwise specified) characteristic symbol test conditions min. typ. 1 max. unit electrical characteristics supply voltage 2 v dd t a = 25c 1.65 ? 3.5 v ?40c t a 85c 1.8 ? 3.5 v output on voltage v out(sat) nmos on, i out = 1 ma ? 100 300 mv v out(high) pmos on, i out = 1 ma v dd ? 300 v dd ? 100 ? mv supply current i dd(en) chip in awake state (enabled) ? ? 2.0 ma i dd(dis) chip in sleep state (disabled) ? ? 8.0 a i dd(av) normal clock mode, v dd = 2.5 v ? ? 71 a normal clock mode, v dd = 3.0 v ? ? 82 a internal chopper stabilization clock frequency f c ? 200 ? khz external_clk and dual_clk pins input current i in v external _ clk = v dd , v dual _ clk = v dd ? 0.5 ? ma external_clk and dual_clk pins leakage current i off v external _ clk = 0 v, v dual _ clk = 0 v ? 0.02 ? a supply slew rate 3 sr t off = 100 ms 0.1 ? ? v/ms normal clock mode characteristics 4 normal mode awake duration t awake_norm ?2538ms normal mode period t period_norm ? 0.7 1.05 ms external clock mode characteristics 4 external_clk and dual_clk pins threshold v th(high) ? ? 0.75 v dd v v th(low) 0.25 v dd ??v external clock mode awake duration t awake_ext v external_clk > v th(high) 38 ? ? ms external clock mode period t period_ext v external_clk > v th(high) 80 ? ? ms state transition delay 5 t delay_ext ?2538ms dual clock mode characteristics 4 dual clock mode awake duration t awake_dual ?2538ms dual clock mode fast sampling period t period_fast ? 8 t awake_dual ?ms dual clock mode slow sampling period t period_slow ?28?ms dual clock mode timeout 6 t timeout ? 100 t period_slow ?ms magnetic characteristics 2 operate point b op south pole to device branded side 5 36 55 g release point b rp north pole to device branded side ?55 ?36 ?5 g hysteresis b hys b op ? b rp ?72110g 1 typical values are at t a = 25c and v dd = 2.75 v. performance may vary for individual units, within the specified maximum and minimum limits. 2 magnetic operate and release points vary with supply voltage. 3 if the device power supply is chopped, power-up slew rate dv dd / dt has to be adjusted to ensure correct functioning of the device. t off is the time of the power cycle when v dd < v dd (min). 4 defined in the functional description section of this datasheet. 5 time between external clock transition and resulting transition of the device between the awake and sleep states. see functiona l description section. 6 if no output transition is detected during the timeout interval, the device goes back into slow sampling. see functional descri ption section.
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance saturation voltage versus supply voltage 0 50 100 150 200 250 300 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v dd (v) v out(sat) (mv) 1.0 2.0 3.0 4.0 1.0 2.0 3.0 4.0 saturation voltage versus temperature 0 50 100 150 200 250 300 -60 -40 -20 0 20 40 60 80 100 t a (c) v out(sat) (mv) average supply current versus temperature 0 10 20 30 40 50 60 70 80 90 100 -60 -40 -20 0 20 40 60 80 100 t a (c) i dd(av) ( a) average supply current versus supply voltage 0 10 20 30 40 50 60 70 80 90 100 1.5 2.5 3.5 v dd (v) i dd(av) ( a) normal mode period versus temperature 0 100 200 300 400 500 600 700 800 900 1000 -60 -40 -20 0 20 40 60 80 100 t a (c) t period ( s) normal mode period versus supply voltage 0 100 200 300 400 500 600 700 800 900 1000 1.5 2.5 3.5 v dd (v) t period ( s) 1.65 1.8 2.5 2.75 3.0 3.5 1.65 1.8 2.5 3.0 3.5 v dd (v) i out = 1 ma v dd (v) t a (c) 1.65 1.8 2.5 3.0 3.5 v dd (v) i out = 1 ma 85c -40c 25c t a (c) 85c -40c 25c t a (c) 85c -40c 25c
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dual mode fast period versus temperature 0 50 100 150 200 250 300 350 400 -60 -40 -20 0 20 40 60 80 100 t a (c) t fast_period ( s) t fast_period ( s) dual mode fast period versus supply voltage 0 50 100 150 200 250 300 350 400 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v dd (v) dual mode slow period versus temperature 0 5 10 15 20 25 30 35 40 45 50 -60 -40 -20 0 20 40 60 80 100 t a (c) t slow_period (ms) t slow_period (ms) dual mode slow period versus supply voltage 0 5 10 15 20 25 30 35 40 45 50 1.0 2.0 3.0 4.0 1.5 2.5 3.5 1.0 2.0 3.0 4.0 1.5 2.5 3.5 v dd (v) operate point versus temperature 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 -60 -40 -20 0 20 40 60 80 100 t a (c) b op (g) operate point versus supply voltage 0 5 10 15 20 25 30 35 40 45 50 55 v cc (v) b op (g) 1.65 1.8 2.5 3.0 3.5 3.5 1.65 1.8 2.5 3.0 3.5 v dd (v) v dd (v) t a (c) 85c -40c 25c t a (c) 85c -40c 25c t a (c) 85c -40c 25c 1.65 1.8 2.5 2.75 3.0 3.5 v dd (v)
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com release point versus temperature -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 b rp (g) release point versus supply voltage -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 b rp (g) hysteresis versus temperature 0 10 20 30 40 50 60 70 80 90 100 110 -60 -40 -20 0 20 40 60 80 100 t a (c) -60 -40 -20 0 20 40 60 80 100 t a (c) b hys (g) hysteresis versus supply voltage 0 10 20 30 40 50 60 70 80 90 100 110 b hys (g) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v dd (v) 1.5 2.5 3.5 1.0 2.0 3.0 4.0 v dd (v) 1.65 1.8 2.5 2.75 3.0 3.5 v dd (v) t a (c) 1.65 1.8 2.5 2.75 3.0 3.5 v dd (v) 85c -40c 25c t a (c) 85c -40c 25c
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description output state operation the output state (vout pin) of this device switches to low (on) when an incident magnetic field, perpendicular to the hall sen- sor, exceeds the operate point threshold, b op . after turn-on, the output voltage is v out(sat) (see figure 2). when the magnetic field is reduced below the release point, b rp , the device output goes high (off), v out(high) . the difference in the magnetic oper- ate and release points is the hysteresis, b hys , of the device. this built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. removal of the magnetic field leaves the device output latched low (on) if the last crossed switchpoint is b op , or latched high (off) if the last crossed switchpoint is b rp . powering-on the device in the hysteresis range (less than b op and higher than b rp ) gives an indeterminate output state. the correct state is attained after the first excursion beyond b op or b rp . micro-power operation micro-power operation of the device involves duty cycle control achieved by: ? powering all circuits in the chip and latching the device output state at the end of awake state periods, and ? turning off the bias current to most circuits in the chip and maintaining the device output state through sleep state periods. this is illustrated in figure 3. the awake state duration, t awake_ x , is common in all defined modes of operation. the sleep state duration is set at a longer duration than the awake period in order to conserve power. during the sleep state, current consumption is insignificant (equal to i dd(dis) ), but the device output does not switch in response to changing incident magnetic fields. the device shows maximum current consumption, i dd(en) , dur- ing the awake state and minimal current consumption, i dd(dis) , during the sleep state. average current, i dd(av) , for micro-power operation is derived from following formula: i dd(av) . i dd(en) t awake_ x + i dd(dis) t sleep_ x = t period_ x three micro-power control modes are available: ? normal clock mode ? external clock mode ? dual clock mode selection of clock mode is determined by the configuration of the external_clk pin and the dual_clk pin, and applied voltages as illustrated in figure 4 and table 1. normal clock mode when both device clock pins are left floating or are grounded, the internal timing circuitry activates the sensor for t awake_norm and deactivates it for the remainder, t sleep , of the duty cycle period, t period_norm . the short awake time figure 2. device output switching logic b op b rp b hys v out(high) (off) v out v out(sat) (on) switch to low switch to high b+ b? 0 v+ figure 3. micro-power behavior of the device 0 t t period_ x t awake_ x t sleep_ x i dd(en) i dd i dd(dis) sample and output latched
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com allows stabilization prior to sensor sampling and data latching on the falling edge of the timing pulse. the output during the sleep time, t sleep , is latched in the last sampled state. external clock mode applying a voltage greater than v th(high) to both clock pins puts the device into the awake state (without automatic cycling through the sleep state). the device uses the maximum defined supply current, reaching maximum power consumption. applying a voltage greater than v th(high) to the external_ clk pin and a voltage lower than v th(low) to the dual_clk pin puts the device into the sleep state (without automatic cycling through the awake state), and latches the device output in the output state determined during the prior awake state. the duration of the awake and sleep periods can be controlled externally by applying a voltage greater than v th(high) to the external_clk pin and applying an external clock to the dual_clk pin. the user can define the input sampling time and frequency to reach a target consumption current level, but the minimum sample time must remain longer than t awake_ext . note that the device should be periodically put into the awake state in order to update the device output state. state transition delay, t ext_delay , appears as the time between an external clock transition and the resulting transition of the device between the awake and the sleep state. this is illustrated in figure 5. dual clock mode when the external_clk pin is left floating, or is grounded, and the dual_clk pin is pulled to a voltage greater than v th(high) , the device enters dual clock mode. figure 6 gives an overview of the device operation algo- rithm in dual clock mode. figure 5. external clock mode clocking; t delay_ext corresponding to the device transition delay into the awake or sleep states after an external clock transition external clocking internal clocking t delay_ext t sleep_ext t awake_ext t delay_ext device awake state device sleep state supply current i dd(en) i dd(dis) table 1. clock mode selection options connection mode description external_clk pin dual_clk pin low / nc low / nc normal clock awake and sleep state durations defined by device internal clock high high external clock, awake state awake and sleep state durations defined by external clock low external clock, sleep state low / nc high dual clock awake and sleep state durations defined by internal fast or slow clock high = v v th(high) , low = v v th(low) , nc = no connect (float or connect to ground) figure 4. clock mode selection algorithm; determined by clock pins connections in the application power on external_clk pin high? yes no external clock mode awake state external clock mode sleep state dual clock mode normal clock mode yes dual_clk pin high? dual_clk pin high? no no yes
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com initially, the device operates in the slow sampling state with a typical sleep time duration, t sleep_slow . the awake time duration, t awake , is common in all defined modes of operation. after the first output state transition, the device switches into the fast sam- pling state, with a sleep time duration, t sleep_fast , of 8 t awake_dual . fast input sampling ensures that the device does not miss any subsequent transitions of the incident magnetic field. this is advantageous in applications such as track ball monitoring, when the track ball can be rotated at very high speeds. if there is no output switching for the duration of the specified timeout, t timeout , then the device switches back into the slow sampling state to conserve battery life in handheld devices. figure 7 shows the case in which the field does not change within the t timeout period. the behavior of the device in the presence of a rapidly changing magnetic field is shown in figure 8. has sleeptimer expired? magnetic field change? returntimer expired ? reset returntimer to t timeout sample magnetic field during t awake_dual yes no update device output dual clock mode initial state set sleeptimer to t sleep_slow set sleeptimer to t sleep_slow set sleeptimer to t sleep_fast no yes yes no figure 6. dual clock mode operation algorithm
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 0 1000 2000 3000 4000 5000 6000 -50 0 50 0 1000 2000 3000 4000 5000 6000 0 1000 2000 3000 4000 5000 6000 0 1000 2000 3000 4000 5000 6000 0 200 400 (ms) (ms) (ms) (ms) magnetic field (g) off on output high low clock supply current ( a) 0100020003000 (ms) (ms) (ms) (ms) 4000 5000 6000 -50 0 50 magnetic field (g) 0 100020003000400050006000 off on output 0 100020003000400050006000 high low clock 0 100020003000400050006000 0 100 200 300 supply current ( a) figure 8. device output response in dual clock mode with a rapid change of the magnetic field figure 7. device output response in dual clock mode with no change of the magnetic field for the duration of t timeout
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application information it is strongly recommended that an external bypass capacitor be connected (in close proximity to the hall sensor) between the supply and ground of the device to reduce both external noise and noise generated by the chopper stabilization technique (0.1 f is a typical value). additionally, it is recommended that, when possible, pins be tied to either the vdd pin or ground potential in order to improve the emc performance of the device. however, it is feasible to float the external_clk and dual_clk pins in the application. in the case where these pins are floating, care should be taken to locate the device as far as possible from system antennas and transceivers. the schematics on this page represent typical application circuits. (a) device is working in normal clock mode. power consump- tion is determined by device internal clock. (b) device is working in dual clock mode. power consumption is determined by device internal clock; frequent usage of device in fast sampling state. (c) device is working in external clock mode; externally-con- trolled power consumption. (d) device is working in external clock mode; high power con- sumption. A1174 dual_clk vdd gnd vout external_clk v bat c bypass A1174 dual_clk vdd gnd vout external_clk v bat c bypass A1174 dual_clk vdd gnd vout external_clk v bat c bypass A1174 dual_clk vdd gnd vout external_clk v bat c bypass (a) (b) (c) (d)
ultrasensitive hall effect latch with internally or externally controlled sample and sleep periods for track ball and scroll wheel applications A1174 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com f f f seating plane 0.38 0.50 0.25 0.70 1.10 1.10 0.30 0.70 1.575 0.50 0.15 1.25 0.325 0.325 2.00 1.00 0.74 1.50 c 0.08 7x c a 1 1 6 6 1 6 a terminal #1 mark area active area depth b f exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) all dimensions nominal, not for tooling use (similar to jedec type 1, mo-229?x2?bcd) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c e reference land pattern layout (reference ipc7351 son50p200x200x80-7-m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) e hall element (not to scale) b pcb layout reference view c d d coplanarity includes exposed thermal pad and terminals copyright ?2008, allegro microsystems, inc. the products described herein are manufactured under one or more of the following u.s. patents: 5,045,920; 5,264,783; 5,442,283 ; 5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com package ew 6-contact mlp/dfn

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